Newsgroups: alt.folklore.computers From: eric@lfs.loral.com (Eric Burch) Subject: Re: Core lattice (was: Re: Wow - This is Great!) Date: Thu, 2 Feb 1995 17:48:44 GMT In article , engine@chac.batnet.com (Kip Crosby) writes: > No coils. There were three STRAIGHT wires through each core, one horizontal > (state wire), one vertical (state wire), and one diagonal (sense wire). Each > state wire carried slightly more than _half_ the current needed to flip the > state of the core (bit), so if _both_ the state wires that intersected in a > single core were charged, the bit would flip. The sense wire then read out > the state. -- kc At first. Soon after you'd get the inhibit line, which ran parallel to one of the coordinate lines, but running current in the opposite direction (to prevent a write-back of a one bit, since all core reads were destructive--adding the inhibit line in made all your sense and write-back electrical pulses the same amount of energy, preserving your electronics. The inhibit pulse needed only to be a fraction of the value of the write-back pulse). Toward the end of the 1960's, circuity was developed that required only two lines per core; one line was used both to select a core, then a fraction of a microsecond later would perform the sense function. -- Eric Burch -- Loral Federal Systems -- Gaithersburg, MD eric@lfs.loral.com usual disclaimers apply imagine a " :-) " after each period above From: engine@chac.batnet.com (Kip Crosby) Newsgroups: alt.folklore.computers Subject: Core lattice (was: Re: Wow - This is Great!) Date: Wed, 1 Feb 1995 10:24:56 LOCAL In article djohnson@tartarus.ucsd.edu (Darin Johnson) writes: >They were little donut magnets (or big, depending upon technology). >Wire coils were wrapped around them, and also they were threaded onto >a wire lattice. The lattice could detect if a donut were magnetized >one direction or the other. The coils were used to flip the state. No. nyet. uh-uh. No coils. There were three STRAIGHT wires through each core, one horizontal (state wire), one vertical (state wire), and one diagonal (sense wire). Each state wire carried slightly more than _half_ the current needed to flip the state of the core (bit), so if _both_ the state wires that intersected in a single core were charged, the bit would flip. The sense wire then read out the state. -- kc From: lstowell@pyrnova.mis.pyramid.com (Lon Stowell) Newsgroups: alt.folklore.computers Subject: Re: Core lattice (was: Re: Wow - This is Great!) Date: 2 Feb 1995 11:59:11 -0800 In article engine@chac.batnet.com (Kip Crosby) writes: > [...The best description yet of mainstream R/W type core memory...] >No. nyet. uh-uh. > >No coils. There were three STRAIGHT wires through each core, one horizontal >(state wire), one vertical (state wire), and one diagonal (sense wire). Each >state wire carried slightly more than _half_ the current needed to flip the >state of the core (bit), so if _both_ the state wires that intersected in a >single core were charged, the bit would flip. The sense wire then read out the >state. -- kc Thus leaving you with a Write-Once, Read-Once type memory. >:-) This is the old destructive read type memory... your memory had then better take all the bits and put them back as they were before you read them. From: scotts@cluon.com (Scott Statton N1GAK) Newsgroups: alt.folklore.computers Subject: Re: Wow - This is Great! Date: 7 Feb 1995 10:02:03 -0800 In article , Dan Hoey wrote: >stangel@netcom.com (Dan Stangel) was the one who asked "if anyone could >explain" how core memory works. > >The sense wires can't detect if the donut is magnetized. They can, >however, detect a _change_ in the magnetization. So the procedure for >reading a core is to flip it in one direction, and see if it changes. >If it changes, you have to flip it back (unless you actually want to >alter the value). > >Dan >Hoey@AIC.NRL.Navy.Mil It is for this reason that many CPUs had read-modify-write cycles. Let's perform a little time line analysis of a read, and a write READ CYCLE 0nS -- CPU requests data for location 12345 from memory controller 200nS -- address decode logic sets up row/column drivers for location & applies write current to set the memory to "000000" 600nS -- Sense amplifiers settle: Data had been 000105, memory controller turns around to put that data back. 1000nS -- memory read cycle complete 1200nS -- data available to CPU WRITE CYCLE 0nS -- CPU requests a write of data 000105 to location 54321 200nS -- address decode logic sets up row/column drivers, & applies write current to set memory to desired value 600nS -- all done READ-MODIFY-WRITE CYCLE 0nS -- CPU requests data for location 12345 from memory controller 200nS -- address decode logic sets up row/column drivers for location & applies write current to set the memory to "000000" 600nS -- Sense amplifiers settle: Data had been 000105, 800nS -- Data available to CPU for read phase; (n) nS pass while CPU performs some function on the data 800nS + n -- memory controller turns around to put that data back. 1200nS + n -- memory RMW cycle complete. If there wre no RMW cycle, the entire process would take 1800 + n nS, rather than the 1200+n nS; These numbers are based on my very hazy memory of the Nova 1200 cycle timings; While the values are wrong, I'm certain, the theory holds. ObAFC: The Nova 1200 memory core planes used a 1A write current between the +15V and -15V rails. 30 WATTS for about a 400nS pulse. 192 microJoules ( 30V * 1A * 400nS * 16 bits) per memory cycle. Scott Statton - N1GAK - Mountain View, CA - scotts@cluon.com GE/CS d-- H+(++) s+:++ g+ p1 au--(----) a28 w+ v++(-) C++++ US++++$ P+ L- 3- E++ N++ K W--- M+ V -po+ Y+ t+ 5 j+ R- G' tv b++ !D B(-) e u+ h++ f+ r+++ n+ y+++(*)